A term you’re likely to hear in reference to program code for network controllers is NE2000-compatible. The NE2000 was an early and popular PC network interface card from Novell. The card contained National Semiconductor’s DP8390 controller. Software for systems that use the ’8390 or a compatible chip has come to be known as NE2000-compatible code. A major feature of the ’8390 is its set of internal registers. By reading and writing to the registers, a CPU can configure the controller, initiate transmitting of data on the network, and read received network data. The registers in the ’8390 are arranged in two 16-byte pages. The CR register is at offset 00h on both pages. Writing to bits 6 and 7 in the CR register selects the current page. Offsets 01h through 0Fh on each page store additional register values. On power-up or reset, program code typically initializes the registers to desired values before Ethernet data transfers begin. An NE2000-compatible chip should support all of the ’8390’s registers. Newer chips generally have additional register pages to support new features.

NE2000-compatible chips are also likely to support accessing buffer memory at addresses 4000h through 7FFFh. A portion of the memory forms a ring buffer for storing data received from the network, and the remainder of the memory stores data to be transmitted on the network. Documentation Many providers of controller chips have example code for setting up the registers and transferring frames. You may need to translate the code for use with a specific CPU. Source and executable code is also available from many vendors of modules that use the chips. The documentation for the original DP8390 can be a useful supplement to the sometimes thin documentation provided for newer NE2000-compatible chips. National Semiconductor also has a couple of application notes. Note AN-475: DP8390 Network Interface Controller: An Introductory Guide, describes the processes of sending and receiving data. Note AN-874: Writing Drivers for the DP8390 NIC Family of Ethernet Controllers, focuses on programming, with example assembly code for a PC. I won’t attempt to duplicate the controllers’ data sheets here. Instead, I’ll concentrate on the features and capabilities that you’ll want to know about in selecting a chip for a project. You can then go to the data sheet for the details.

The ASIX AX88796

An Ethernet controller designed for use in embedded systems is the AX88796 3-in-1 Local Bus Fast Ethernet Controller from ASIX Electonics Corporation. Rabbit Semiconductor uses this controller in its RCM3200 module. The controller supports Ethernet communications at 10 and 100 Mb/s. The ’88796 is NE2000-compatible. A major difference between the ’88796 and the DP8390 is that the ’88796 has an on-chip 16-kilobyte static RAM (SRAM) buffer for network data. The ’88796 also has separate (not multiplexed) data and address buses and an interface to serial EEPROM.

Connections

Ethernet. For twisted-pair networks, the chip can connect through a filter to an RJ-45 jack. The RCM3200 uses a PulseJack module from Pulse Engineering, Inc. The module integrates the RJ-45 connector and filtering circuits in a single package. An on-chip MII enables using an external PHY to connect to other cable types at 10 or 100 Mb/s. Bus Compatibility. The CPU0 and CPU1 pins configure the chip for use with one of four bus types that are popular in embedded systems: ISA, Intel 80186, Intel MCS-51 (8051), and Motorola 68000. The selected bus determines the functions of the pins that control reading and writing to the external data bus and the polarity of the interrupt output. For example, on a 68000 bus, pin 18 is a R/W input that controls bus reads and writes and pin 19 has no connection, while the ISA interface has separate read and write signals: pin 18 is IOWR and pin 19 is IORD. SRAM. The controller’s 16-kilobyte SRAM buffer holds packets waiting to transmit on the network and packets received from the network.

With an 8-bit data bus, only 8 kilobytes of the SRAM are available. Addressing. The chip has 10 address inputs, but not all systems need them all. The first five bits (SA0 through SA4) address the controller’s internal registers. Every controller must have these lines connected to the CPU’s address bus. Two of the registers (10h, 11h) are the Data Port, which enables the CPU to access the controller’s 16 kilobytes of SRAM without using additional address lines. In most systems, the Ethernet controller shares the data bus with other components, so the CPU needs a way to select the controller on the bus. Two ways to accomplish this are by using additional address lines to select a base address or by using the controller’s Chip Select (/CS) input. The 10-BASE0, 10-BASE1, and 10-BASE2 pins on the ’88796 can select one of eight base addresses. Jumpers or CPU outputs can control the pins, or they can be hard-wired. The address values are compatible with PC hardware, but there’s no reason you can’t use them in other systems. For example, if the controller has a base address of 200h, the CPU accesses the chip’s registers by reading and writing to the addresses 200h through 21Fh.

To enable selecting the chip by address, the controller’s address pins SA5 through SA9 must connect to the CPU’s address bus. If you instead use the Chip Select input to select the chip, you don’t need to connect the controller’s upper address lines to the bus, and you can select a base address in a higher address range than the options programmed into the chip. Rabbit Semiconductor’s RCM3200 module uses the Chip Select along with firmware that configures the Rabbit 3000 CPU to strobe a port bit on I/O accesses to a specific address range. When using Chip Select, SA5 through SA9 must match the selected base address in the controller. The RCM3200 module permanently enables base address 200h by tying SA9 high and tying SA5 through SA8 low at the controller. Data. A register bit in the ’88796 selects whether the controller uses 8 or 16 data lines. The data bus for the 68000 mode must be 16 bits, but the other buses can use 8 or 16 bits. Interrupts. The IRQ interrupt output can request service from the CPU. The polarity of the signal depends on the selected bus type. A CPU that doesn’t support or doesn’t want to use interrupts can poll the interrupt line. Serial EEPROM Interface. The ’88796 has four pins that can interface to a serial EEPROM with a Microwire interface. The EEPROM can provide non-volatile storage for an Ethernet hardware address and other information. Unlike some other controllers, the ’88796 doesn’t automatically load information from the serial EEPROM into the controller’s registers. Instead, the CPU must access the EEPROM’s contents by reading and writing to the MII/EEPROM Management Register. The CPU can then copy the information it reads from the EEPROM to other registers.

If your system already has Flash memory or other non-volatile, read/write memory, you can save on component cost by using existing memory to store the configuration data instead of a serial EEPROM. This is the approach Rabbit Semiconductor uses in its RCM3200 module.

Transferring Data

Like the DP8390, the ’88796 uses direct memory access (DMA) to automate transfers of network data into and out of the SRAM. The CPU reads and writes to the Data Port register, and the controller stores or retrieves the data at sequential addresses in the SRAM. Receiving data. The ’88796 stores data received from the network in a portion of the chip’s SRAM reserved as a ring buffer. In a ring buffer, two pointers determine where to read and write next. The write pointer increments after each write to the buffer. After writing to the highest address, the pointer wraps back to the lowest address, forming a ring. Meanwhile, as the CPU reads the data from the buffer, the read pointer steps through the buffer in a similar way. To prevent lost data, the CPU must retrieve the data fast enough to keep the buffer from overflowing. In the ’88796, the Page Start Address Register (PSTART) and Page Stop Address Register (PSTOP) determine the buffer’s size. Typically, half or more of the SRAM is reserved for the ring buffer, with the remainder left for the transmit buffer. The ring buffer is structured as a series of 256-byte buffers, or pages. The Boundary Pointer register (BNRY) is the read pointer, which holds the page address of the next data packet for the CPU to read.

The Current Page Register (CPR) is the write pointer, which holds the page address for storing the next data packet received from the network. In storing a frame in the ring buffer, the controller reserves the first four bytes for storing the contents of the Receive Status Register (RSR), the address of the next packet to be stored in the buffer, and the number of bytes received. The SRAM stores a received frame only if the destination address matches the controller’s hardware address or another address the controller is configured to accept. The Physical Address Registers (PAR0–PAR5) contain the interface’s Ethernet hardware address. In addition, the controller accepts frames sent to a multicast address specified in the controller’s Multicast Address Registers (MAR0–MAR7), and the controller accepts broadcast transmissions if the Accept Broadcast (AS) bit is set in the Receive Configuration Register (RCR). The Receive Configuration Register also permits configuring the chip in promiscuous mode, which causes the controller to accept frames with any destination address. On receiving a frame, the controller checks for CRC and frame-alignment errors and checks to be sure the frame is at least the minimum allowed frame size. The controller drops any frame that shows an error or isn’t the minimum size. When the contents of a frame are available in the ring buffer, the controller asserts an interrupt. The CPU can then use the controller’s Remote Read command to retrieve the data from the ring buffer. The CPU reads all of the data from a single DMA-port address (10h) and the controller provides the bytes in sequence. Sending data. Sending data on the network requires two steps: the CPU first copies the data to send to the SRAM and then instructs the controller to send the frame on the network. The CPU uses the controller’s Remote Write command to write the data to transmit to the controller’s SRAM. The CPU writes all of the data to the DMA-port address (10h), and the controller stores the bytes in sequence. Transmitting doesn’t use a ring buffer because the CPU can control the transfer of data into the buffer. After copying data to send to the SRAM, the CPU writes the starting page address of the data to the Transmit Page Start Register (TPSR) and writes the number of bytes to transmit to the Transmit Byte Count Registers (TBCR0, TCBCR1).

When the CPU sets the TXP bit in the Command Register, the controller sends the specified bytes in a frame on the network. The controller adds the preamble, start-of-frame delimiter, and CRC values in the appropriate locations in the Ethernet frame to be transmitted. The controller also decides when to attempt to send the frame on the network, sends the bits to the network interface in sequence, and handles collisions and retries. When a transmission is complete, an interrupt informs the CPU so it can prepare another frame to send or take other action.